1. Field of the Invention
The present invention relates to a DMA (direct memory access) controller, and more specifically to a DMA controller used in a microcomputer system for transferring data between a memory and an I/O (input/output) device.
2. Description of Related Art
In a conventional microcomputer system, a DMA controller for controlling a direct data transfer between a memory and an I/O device which are coupled in common to a data bus, includes a data counter, an address counter and a read/write controller.
When the read/write controller receives a DMA request from the I/O device, the read/write controller outputs a DMA acknowledge to the I/O device, and at the same time, outputs read/write control signals to the memory and the I/O device, respectively. For example, when data is transferred from the memory to the I/O device, the read/write controller outputs a read control signal and a write control signal to the memory and the I/O device, respectively. To the contrary, when data is transferred from the I/O device to the memory, the read/write controller outputs a read control signal and a write control signal to the I/O device and the memory, respectively.
On the other hand, when the DMA is requested, the DMA controller, particularly the data counter and the address counter are initialized by a CPU (central processing unit) included in the microcomputer system. In the course of the DMA operation, the read/write controller decrements the data counter, and increments or decrements the address counter. A content of the address counter is supplied to the memory as an address to be accessed.
Thus, a large amount of data can be directly transferred between the memory and the I/O device through the data bus but without the intermediary of the CPU.
When the content of the data counter becomes zero, the data counter outputs a data transfer stop signal to the read/write controller so as to stop operation of the read/write controller.
In the above mentioned conventional DMA controller, if a memory area not to be read or written exists between a data transfer start address and a data transfer end address in the memory, it is necessary to stop the data transfer just before the memory area not to be read or written, and then, to initialize the DMA controller, again, so that the data transfer is restarted just after the memory area not to be read or written. However, as mentioned above, the initialization of the DMA controller is executed by the CPU, an extra load is given to the CPU in the course of the data transfer in the DMA mode. As a result, a system efficiency of the microcomputer is decreased.